专利名称：Method and Apparatus for Testing an
Integrated Circuit
发明人：Kedarnath Balakrishnan,Seongmoon
Wang,Wenlong Wei,Srimat T. Chakradhar
申请号：US11692367申请日：20070328
公开号：US20070266283A1公开日：20071115
专利附图：
摘要：Disclosed is an apparatus and method for testing an IC having a plurality of scanchains. A test input is transmitted over a tester channel to at least one scan chain during a
time interval. Specifically, a memory element stores a first test input transmitted during afirst time interval and a combinational circuit connected to the memory element and scanchain transmits to the scan chain one of a) the first test input and b) a second test inputtransmitted over the tester channel during a second time interval occurring after the firsttime interval.
申请人：Kedarnath Balakrishnan,Seongmoon Wang,Wenlong Wei,Srimat T. Chakradhar
地址：Austin TX US,Plainsboro NJ US,Mercerville NJ US,Manalapan NJ US
国籍：US,US,US,US
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